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Hi!

I am currently reading the documentation of my chipset. In various places in the paper I found the TOM term. But there is no one regiser that show where this TOM is exactly. What I have understood is that TOM can be obtained from DRB0-7, but this seems very confusing to me. I wonder if somebody can give me some link to some easy to understand and in the same time well explained paper about this DRBs. I dont know if I can simply rely on the BIOS e820 to do this. If so, where the TOM should be in one system with 2GB-on the top of these 2GB or on the top of the 4GB?
Apparently my poor understanding of the theme make me unable to formulate an clear question.

Cheers!

Hi,

smoothCoder wrote:I am currently reading the documentation of my chipset. In various places in the paper I found the TOM term. But there is no one regiser that show where this TOM is exactly. What I have understood is that TOM can be obtained from DRB0-7, but this seems very confusing to me.

For recent AMD CPUs (with hyper-transport) there's 2 "Top Of Memory" registers - one for the top of memory below 4 GiB, and one for the top of memory above 4 GiB. For both of them, they only say the top of memory and they do not say the top of usable memory (because different areas can be used by the firmware and/or chipset for special purposes, like e.g. "ACPI NV-RAM"). These registers are part of the memory controller, and are intended to be used to assist the CPU when figuring out which hyper-transport link to forward accesses to. They're not intended for programmers (or OS developers).

For recent Intel CPUs (that use Quickpath) there's probably something slightly similar in the CPU's memory controller/s. For older AMD CPUs and older Intel CPUs, there's probably something slightly similar in the chipset's memory controller.

In almost all cases you need to use "int 0x15, eax=0xE820". Partly because you want to know the difference between "reserved RAM" and "usable RAM", and partly because you don't want to write different code for each CPU and/or chipset and deal with bugs you can't test.

Even if you're writing your own firmware for a recent AMD system, you still wouldn't read from the TOM registers - instead you'd do RAM size detection (on each CPU/chip/memory controller) and then configure the memory controller registers to suit what you detected (basically, you'd be setting the TOM registers, not reading from them).


Cheers,

Brendan

Thanks, Brendan!

Brendan wrote:They're not intended for programmers (or OS developers).

I'm glad to know that for normal chipset driver I have not to deal with these DRB stuff.

In much documents in internet people say that almost all SMRAMs appears re-mapped by BIOS at 0A0000h. But I want to support the rare case when SMRAM are maped to hight memory. In my chipset documentation is easy to detect when SMRAM appears in hight memory and is easy to calculate it. The problem is to find TOM itself. But due the fact I found SMRAM on my hypervisor not initialized nor used, I thing to initialize it to hight RAM, and set the B_OPEN to 0, then clear the error bit E_SMRAM_ERR if set and try to read from the place I suspect to be interpreted by the chipsed as TOM. If on some of this reads error bit sets, I will assume there is TOM. I thing to try this just to find out where the chipset place the TOM with diferent amounts of available memory. Hopefully this will be valid for other model of chipsets too. And even more hopefully, no one of the hardware that I use will use SMM, in such case I just will lock the empty SMRAM and leave it unutilized.

Cheers!