PCI I/O address space matching

[thorfdbg]

Hopefully, someone can help me here, as I still have a kind of twist in my head concerning I/O space access over PCI (yes, that's all legacy...).

With PCI, we have BAR addresses that define on which addresses a particular device reacts when the address is put on the PCI bus. Now, bit 0 of the BAR register defines whether an address is I/O or memory mapped, and hence - I suppose - on x86 whether a BAR is reached by "in" and "out" instructions (when read in I/O space) or with the usual "ld" when reading memory space. This kind of mapping needs to be done by the PCI host bridge, I assume.

Now, the BAR is 32 (or even 64) bit wide, whereas the x86 (legacy) IO space is only 16 bit wide. So how does a device match an address triggered by an "in" or "out" instruction which delivers only 16 bits of an address. Does the PCI host bridge have to "invent" the upper 16 bits? And if so, how does an algorithm programming the BAR register know which values to put there? Or do devices react on "I/O" accesses simply ignore the 16 MSBs of an address?

Thanks!

[Octocontrabass]

Does the PCI host bridge have to "invent" the upper 16 bits? [...] Or do devices react on "I/O" accesses simply ignore the 16 MSBs of an address?

Neither. When accessing I/O space, the CPU provides zeroes in the upper address bits.