topic is cut into two parts and now its totally pointless

[Geri]

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[iansjack]

on a 3 ghz superscalar 2 core SUBLEQ cpu ... no synthetic benchmarking however - all of this is measured in REAL workloads

Could you let us know the manufacturer and model number of this CPU on which you are performing REAL measurements? Where could I buy one and how much would it cost me?

this may seem very bad compared to x86 os-es

Then I hope this processor is really cheap. Otherwise, why would I not just use an x86?

[dozniak]

superscalar subleq... now this is deep

[Geri]

-i multiplied the results of an emulated subleq cpu (400 million instruction per sec) with 20, to get values of a =3 ghz & 2.66 instruction per clock cpu.

-i also compiled the code for x86 (athlon2 x4 3,1 ghz) and emulated only the hardware io for subleq to check if i get the same performance.

-both showed approx the same performance.

-i also tested natively on a 1,6 ghz ht atom (but didnt measured, i only checked how much it stutters)

-performance scaling linearly with the raw instruction per sec, but the sheduler and disk io will be also clamped by the io performance.

[iansjack]

all of this is measured in REAL workloads

i multiplied the results of an emulated subleq cpu (400 million instruction per sec) with 20, to get values of a =3 ghz & 2.66 instruction per clock cpu

So the claim to measure REAL workloads was just b/s?

But, even were it true, your results seem to show that I would get better performance out of an x86. Much better, considering that the subleq CPU doesn't actually exist.

I think I'll stick with a REAL processor.

[Geri]

there is no dawn-compatible subleq cpu yet, i cant measure it on native subleq cpu, only on emulated, the workload is still real (for example i measured the file system speed by creating a browsable article database consisting tens of tousands of articles).

yes, you can write more efficient operating systems on platforms with actual hardware support for interrupts, dma and signal processing. but i cant add those to subleq, it will ruin the simplicity of the hardware. however, the overall real-world performance will not be as big as you expect even if you have hardware acceleration for everything. even windows and linux sheduler is cycling on a few ten khz.

[iansjack]

You make some very convincing arguments of why a subleq processor would be inferior. (Which may explain why no-one manufacturers them.) I can only agree with you.

[Geri]

subleq cpu have major advantages and disadvantages (just like any other architecture).

[iansjack]

But you tell me it's performance would not be as good as an x86. So what "advantages" would persuade me to use one? And why does no-one manufacturers them?

[Brendan]

Hi,

subleq cpu have major advantages and disadvantages (just like any other architecture).

SUBLEQ only has major disadvantages.

"Seems simple (to people that lack knowledge and experience)" is just one of the disadvantages.


Cheers,

Brendan

[hgoel]

Now that I think about it, how would a superscalar subleq design work? How can the processor tell if an instruction depends on a previous as of yet unexecuted instruction without having to actually execute all instructions up to that point? Although, even x86 would suffer from this issue in memory references, so how do they determine if an instruction that relies on a memory access isn't dependent on an unexecuted instruction? The only approach I can think of is that they don't and instead just drop the result if it turns out that the memory content has changed due to another instruction.

[Geri]

brendan: autising above a propriretrary hardware obfuscator (like x86) is not knowledge. also after the topic has been splitted, i removed the original post, it makes no point, and inspires an opinion i would not even agree.

[Geri]

hgoel: you can do 3 things for a superscalar subleq design:

1. you blindly execute the instructions parallelly, and you only write the results out if your circuits detecting independency of the instructions (you throw out the other results).

2. you design a long pipeline that executes (unifys) a lot of instructions after each other. this needs a lot of connects into the cache to have a lot of cache reads in a cycle.

3. do both

method 2. resuires more transistors than 1. method. method 3 requires more transistor than method 2.

with an inorder superscalar subleq cpu you can parallerize up to typically 2 instructions. out of order superscalar should be able to do 10-20.

[Kazinsal]

Have you considered that maybe no one wants to see your incessant shitposting and that's why when you get fully hot and heavy about your idiosyncratic ideas about ISA design everyone tunes out and your posts get split off to wither away and die?

[Geri]

no. my system is good, and i am poroud of it.