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That's a crazy question : is there anybody here that would have heard of some architecture with a "skip TLB" feature, as well as the OS able to handle that of course ?
I was thinking to - not small - embedded systems : all critical code & data (including kernel space) would be accessed via the "skip TLB" unlikely stuff, while other more standard apps would be addressed via the good old TLB hit.
That's a crazy question : is there anybody here that would have heard of some architecture with a "skip TLB" feature, as well as the OS able to handle that of course ?
I was thinking to - not small - embedded systems : all critical code & data (including kernel space) would be accessed via the "skip TLB" unlikely stuff, while other more standard apps would be addressed via the good old TLB hit.
Telenn
The TLB is a cache for page translations. By 'skipping' the TLB you slow down page translations. Is this what you really want ?
Perhaps by 'skip TLB' you mean that some entries are more likely to remain in the TLB and aren't removed when the TLB is flushed ?
If a trainstation is where trains stop, what is a workstation ?
Well actually, page translations slow down the system, as a piece of this Rube Goldberg contraption that we call Virtual Memory...
...Ok, ok, stop throw it away. It does sound for sure provocative, retrograde, or whatever you want. Virtual Memory of course have many many advantages, but actually it does not always match your performance needs. From small embedded systems without MMU, to ZeptoOs which provides a big hugepage backed memory area that eliminates TLB misses, many systems already avoid or minimize the overhead of the Virtual Memory machinery... with some drawbacks of course.
So I was thinking to an hypothetic solution (OS + hardware) able to mix both of the two worlds, let's say for the need of a not so small embedded system :
- the MMU would always be enabled, as usual,
- standard non critical apps would be mapped as usual,
- but specialized critical apps (as well as the kernel) would be addressed directly without any translation : a big contiguous memory area would be reserved, for which virtual addresses would have a direct equivalence to physical ones, and thus for which the MMU would have been able to "skip the TLB".
Also, I guess some ELF change would be necessary...
I see the embed electronics improve in speed every day, and the need for squeeze out the last cycle (if it actually out-weight the induced complexity, but usually not) is increasing at the negative time direction.
Anyway, you may want to look into ARM, that you have total control on the TLB.
If you want to skip page translation instead, no, it means to have different behavior on different address zone and is usually lead to system design troubles.
