Simulated Memory Protection, Paging with 8086

[deadmutex]

I was thinking about building a non-pc system from scratch as a hobby project. One problem that I have with intel processors from the 286 upwards is the inability to turn on/off memory protection. After a little thought, I realized that the address bus could be scanned for invalid addresses and the processor could be interrupted. From a hardware perspective, is it possible to simulate protection, paging, user/supervisor modes with an 8086 or 80186 by tinkering with i/o devices?

[qw]

MMU's are not necessarily integrated into the CPU, so I guess it is possible. Don't know if there is an MMU that works with the 8086 though.

[Combuster]

The problem with an 8086 (and from the looks of it, all other *86 chips) is that it lacks an bus error line that can abort running memory operations, so you can't implement an external pagefault without losing processor state. If that can't bother you, the NMI line is probably the best way to force an error. Otherwise, you might want to consider using a 68010 processor instead (which is also available in a hobbyist-friendly formfactor)